Skip to content

Pull requests: llvm/circt

New pull request New
201 Open 7,243 Closed
201 Open 7,243 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

[FIRRTLToHW] Fix crash when lowering instance_choice with clock outputs
#9941 opened Mar 14, 2026 by seldridge • Draft
[Synth] Add basic SAT construction for functional reduction
#9939 opened Mar 14, 2026 by uenoku Loading…
[FIRRTL] Add lowering for firrtl.domain.subfield operations
#9933 opened Mar 13, 2026 by seldridge Loading…
4
[ImportVerilog] Fix moore.conversion legalization failure on interface ports
#9927 opened Mar 13, 2026 by Mohamed-Khairy-SWE Loading…
[HWToBTOR2] Add basic support for verif.formal
#9926 opened Mar 13, 2026 by dobios Loading…
[ImportVerilog] Convert arity-based system task to named-based matching ImportVerilog
#9923 opened Mar 12, 2026 by fabianschuiki Loading…
4
[RTG][circt-tblgen] Add backend to list instructions RTG Involving the `rtg` dialect
#9922 opened Mar 12, 2026 by maerhart Loading…
1
ImportVerilog: add step-1 SV interface import
#9904 opened Mar 11, 2026 by AmurG Loading…
1
[SV] Add sv.macro_instance operation
#9900 opened Mar 10, 2026 by uenoku • Draft
3
[FIRRTL] Add configuration file support for FIRRTL instance choices
#9870 opened Mar 7, 2026 by uenoku Loading…
2
[LTL] Make ltl.delay support optional clocking
#9869 opened Mar 7, 2026 by Clo91eaf Loading…
11
[ImportVerilog] Introduce the semantic analysis of slang
#9862 opened Mar 6, 2026 by sunhailong2001 Loading…
14
[Synth] Implement operation reuse for LowerVariadic
#9850 opened Mar 5, 2026 by joaovam Loading…
14
[FIRRTL] Support probe ports in instance_choice operations
#9815 opened Mar 3, 2026 by uenoku • Draft
1
[circt-bmc] Add multi-clock BMC support via independent toggling
#9803 opened Mar 1, 2026 by robert-at-pretension-io • Draft
[circt-bmc] Add verif.contract support
#9800 opened Mar 1, 2026 by robert-at-pretension-io • Draft
1
[ImportVerilog] Implement procedural continuous assignment
#9795 opened Mar 1, 2026 by Arya-Golkari Loading…
6
[LLHD] Allow verif ops in comb canonicalization
#9752 opened Feb 25, 2026 by towoe Loading…
4
[HW] HWVectorization Part 3: Structural Patterns
#9749 opened Feb 24, 2026 by mafeguimaraes Loading…
6
Migrated to PyConcrete* base classes
#9745 opened Feb 24, 2026 by jpienaar Loading…
10
[FIRRTL] Add CheckInstanceChoice pass to reject nested instance choices
#9743 opened Feb 24, 2026 by uenoku Loading…
5
fix: handle null cases for global memref
#9738 opened Feb 23, 2026 by Abhilekhgautam Loading…
1
[FIRRTL][InferResets] Only create reset ports for modules that need them
#9736 opened Feb 23, 2026 by seldridge • Draft
[RTGTest] Remove RV instructions RTG Involving the `rtg` dialect
#9732 opened Feb 23, 2026 by maerhart Loading…
1
[LTLToCore] Lower LTL delay/clock patterns to core logic
#9722 opened Feb 22, 2026 by robert-at-pretension-io Loading…
12
ProTip! Filter pull requests by the default branch with base:main.