[CuTe] adding DSL INT8 MMA support on SM80+, with CuTe C++ example#3097
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ayghri wants to merge 2 commits intoNVIDIA:mainfrom
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[CuTe] adding DSL INT8 MMA support on SM80+, with CuTe C++ example#3097ayghri wants to merge 2 commits intoNVIDIA:mainfrom
ayghri wants to merge 2 commits intoNVIDIA:mainfrom
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This PR adds INT8 warp-level MMA with an Ampere batched GEMM example. Partial solution to #3081
MmaI8OpandMmaIntOverflowinpython/CuTeDSL/cutlass/cute/nvgpu/warp/mma.py, wrapsmma.sync.alignedwith.s8/.u8qualifiers, shapes (16,8,16) and(16,8,32), saturate/wrap overflow modes.
examples/python/CuTeDSL/ampere/tensorop_gemm_i8.py. Followstensorop_gemm.pyconventions.examples/cute/tutorial/igemm_sm80.cu. CuTE C++ implementation, followssgemm_sm80.cu.What works:
--b_dtypeU8 kept for future IR supportWhat does not work:
INT8 vs FP16 differences:
ldmatrixrequires 128-bit aligned smem. FP16column-major gives 8×16b = 128 bits; INT8 column-major gives 8×8b = 64 bits.
MBase=4(not 3) because
log2(128/8) = 4.64KB, limiting occupancy to 1 CTA/SM (for my RTX 3090, I haven't benchmarked on A100 yet).
Performance vs PyTorch 2.9.1+cu128 (
torch._int_mm), RTX 3090100 iterations, CUDA event timing, TOPS = 2MN*K/time.
N = K = 4096
N = K = 16384
Non-aligned dimensions
Testing