From 94cd4261c899a29d9084c699f525e61c2bb84af0 Mon Sep 17 00:00:00 2001 From: nope Date: Wed, 4 Feb 2026 16:57:37 +0800 Subject: [PATCH] arch/esp32s3/dma: Fix data transmission failure when buffer is in PSRAM PSRAM buffers require explicit cache management when used with DMA, as DMA accesses physical memory directly, bypassing the CPU cache. Before starting DMA transfer: - For an **OUTGOING** transfer (PSRAM -> Device): Call `cache_writeback_addr()` to flush dirty data from cache to PSRAM. - For an **INCOMING** transfer (Device -> PSRAM): Call `cache_invalidate_addr()` to invalidate cache lines, ensuring DMA can write to PSRAM. This ensures cache coherence and correct data transmission in burst mode. Signed-off-by: liu --- arch/xtensa/src/esp32s3/esp32s3_dma.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/xtensa/src/esp32s3/esp32s3_dma.c b/arch/xtensa/src/esp32s3/esp32s3_dma.c index 81310b8feda7b..b0653b90f0427 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_dma.c +++ b/arch/xtensa/src/esp32s3/esp32s3_dma.c @@ -285,11 +285,16 @@ uint32_t esp32s3_dma_setup(struct esp32s3_dmadesc_s *dmadesc, uint32_t num, } dma_size = 0x1000 - alignment; + cache_invalidate_addr(pdata, bytes); } else if(!tx && burst_en) { dma_size = ESP32S3_DMA_BUFLEN_MAX_4B_ALIGNED; } + else if(tx && buffer_in_psram) + { + cache_writeback_addr(pdata, bytes); + } for (i = 0; i < num; i++) {